Samsung Electronics has announced that it has started initial production of chips using a new optimized 3nm process, using a Gate-All-Around (GAA) transistor architecture.
GAA transistor architecture uses gates wrapped on all four sides of the ultrathin channels. This improves gate control, and performance, by overcoming physical scaling limitations of the traditional Fin Field-Effect Transistor (FinFET) architecture currently being used in chips.
Samsung says GAA also allows them to improve power efficiency by reducing the amount of voltage supplied within the chip. It also increases performance by increasing drive current capabilities.
The Korean technology and hardware giant says that it is starting the first application of the new process, with chips designed for high performance and low power computing applications. It also plans to expand the process to mobile processors.
“Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry’s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics.
“We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology,” Choi added.
Compared to the 5nm process, the first generation 3nm nodes with GAA reduce power consumption by up to 45%, and is 23% faster in performance. It also has a 16% smaller surface area. Samsung says that the second generation 3nm nodes will improve performance by up to 30%, while reducing power requirements by 50%. It will also have a 35% smaller surface area.
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