India aims to manufacture 3 nm and 2 nm chips by 2032: Ashwini Vaishnaw

Ashwini Vaishnaw said the government’s original approach of providing EDA tools, IP access and multi-project wafer (MPW) support had been validated by the progress made so far.

• India targets 3nm chip manufacturing by 2032 and 2nm by early 2030s
• Semicon 2.0 to focus on six core chip categories for strategic sectors
• Government aims to scale DLI startups to 50 fabless companies in next phase

Did our AI summary help?

India is aiming to manufacture 3 nanometre and eventually 2 nanometre chips by the early 2030s, as part of the next phase of its semiconductor programme, Union IT minister Ashwini Vaishnaw said while interacting with startups approved under the Design Linked Incentive (DLI) scheme on January 27.

“As we go into 2029, we will have a major capability of manufacturing and designing the chips which are required practically in 70–75 per cent of all applications in our country. The next level should come by 2032… to reach 3nm chips manufacturing,” Vaishnaw said.

He added that the roadmap to reach 3nm and 2nm manufacturing would be a core pillar of Semicon 2.0, drawing lessons from how South Korea, Taiwan and Japan built their chip ecosystems.

Speaking at the event showcasing DLI 1.0 startups, Vaishnaw said the government’s original approach of providing EDA tools, IP access and multi-project wafer (MPW) support had been validated by the progress made so far.

“So many of you (startups) have taped out and validated your products. Many of you have found markets,” he said.

India has 24 startups under DLI and that the next phase aims to scale this to at least 50 fabless companies.

Under DLI 2.0, which will be rolled into Semicon 2.0, the government plans to concentrate support around six core chip categories: compute, RF, networking, power management, sensors and memory.

“With these six, we can build any major system — whether it is defence, missiles, railways or automobiles,” Vaishnaw said.

He also indicated that tape-out facilities for mature nodes such as 180 nm would be anchored at SCL Mohali, while nodes down to 28 nm would be supported through the upcoming Tata fab in Dholera.

The minister said inputs from startups under DLI 1.0 would directly influence the design of the next scheme, including what should and should not be supported.

At the event, several founders flagged the need for stronger backing for analog and RF IP, preferential market access in strategic sectors, and help in bridging cost until volumes scale up.

Startups at the event showcased chips already in tape-out or testing stages across AI, RF and broadband domains.

Trivandrum-based Netra Semiconductor said its A2000 AI application processor taped out on TSMC’s 12 nm node in October and is now undergoing silicon testing, while its R1000 AI-MCU is expected to tape out next month.

Fermionix, an RF IC startup, highlighted demand from defence and satellite communications customers for its X-band radar chips and sought government support to expand into Ku- and Ka-band products.

InCore Semiconductor, founded by the creators of IIT-Madras’ SHAKTI processor, reiterated its push for RISC-V solutions and preferential market access in critical sectors.

Vaishnaw also announced that the government will institute Deep Tech Awards in 2026 across sectors such as semiconductors, AI, space and biotech.

“With Semicon 2.0, we will have a major part of the programme dedicated to reaching the 3nm and 2nm goal. By 2035, we should be among the top four semiconductor nations in the world,” he said.