The government is likely to boost the fiscal outlay for the design-linked incentive (DLI) scheme under the second phase of the India Semiconductor Mission (ISM), aiming to bolster the indigenous chip-design ecosystem by extending sops to companies that have moved beyond the startup stage, such as Zoho, Kaynes, and L&T Semiconductors Technologies, a government official said.
The existing DLI scheme, part of the $10-billion sops package for the semiconductor ecosystem, is limited to Indian startups, although multinational companies have urged the government to extend fiscal support to them as well.
The government allocated Rs 1,000 crore for the first phase of the scheme, which will provide financial incentives and infrastructure support over five years for developing and deploying semiconductor designs for integrated circuits, chipsets, and system-on-chips.
“In ISM 2.0, we will increase the corpus for DLI to include large Indian companies. The ministry will also increase the reimbursement on various applications across categories in Phase-2,” a senior IT ministry official told Moneycontrol.
The official said that after consulting with startups and stakeholders, the ministry believes the existing incentives are low and must be increased. “Basis our consultation, the ministry believes that large companies should also leverage the policy for which the outlay will be increased,” he added.
The government is also likely to add a condition that the companies must ensure the chip design's intellectual property (IP) remains in India to be eligible for the incentive.
The Ministry of Electronics and IT (MeitY) has approved chip design-related proposals from at least 12 Indian startups and committed more than Rs 130 crore to their projects. It has received 59 applications, 12 of which have been cleared for financial assistance, and 21 are under review.
The government aims to provide funding for at least 100 startups over the course of five years through the DLI scheme, averaging 20 startups per year.
Under the existing scheme, the government provides for reimbursement of up to Rs 30 lakh per application for MPW (multi-project wafer) fabrication of design and post-silicon validation activities; reimbursement of up to 50 percent of the eligible expenditure subject to a ceiling of Rs 15 crore per application for designing semiconductor goods; and reimbursement of 6-4 percent of net sales of designed semiconductor goods over five years, subject to a ceiling of Rs 30 crore.
Another official mentioned that the ministry believes design-related incentives should only be given to Indian companies. Any requests for support from multinational companies will not be considered. “There are demands from several companies to apply for the DLI scheme. However, the government has not been convinced since there will be issues around the ownership of intellectual properties (IP) and their origins,” he added.
India is a significant player in chip designing, hosting design offices for major semiconductor companies. However, the Indian engineering workforce has historically focused on designing systems for foreign companies, leading to minimal intellectual property creation by Indian entities.
The US-based chipmakers like NXP Semiconductors, Qualcomm, and MediaTek intended to apply for the DLI scheme once the government opened it up to multinational companies. These companies' large chip design centres in India support their global design operations.
Last week, at the Semicon 2024 event in Greater Noida, Electronics and Information Technology Minister Ashwini Vaishnaw said the government is preparing to launch the second phase of the India Semiconductor Mission. This mission will expand efforts beyond semiconductor fabrication and chip packaging units to include component companies and other key players in the ecosystem. The government will also focus on increasing the availability of raw materials, including gases.
The introduction of the second phase, which may receive a budgetary allocation of up to $ 10 billion, is expected to take three to four months.
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