California-based Cadence Design Systems plans to collaborate with the Indian government and domestic chipmakers to develop and design indigenous graphics processing units (GPUs), which are seeing a huge demand spike for the role they play in artificial intelligence (AI).
Designing and developing a GPU, however, will take at least four to five years and local manufacturing will take even longer due to the absence of advanced production capabilities, Cadence India managing director Jaswinder Ahuja has told Moneycontrol.
“If India were to start developing its own GPU today, a production-ready version would realistically take at least that long (three to five years),” Ahuja said. “This means the government’s strategy should align with its approach in other areas, initially relying on imports and partnerships with key providers like Nvidia and AMD.”
GPUs are vital for AI as they can handle many tasks at once, making them much faster than regular computer processors. This speed is crucial for training and running AI models, which need to process large amounts of data quickly.
The government is talking to global chip giants such as Nvidia, Advanced Micro Devices (AMD), and Hewlett Packard Enterprise (HPE) to develop indigenous GPUs.
Union minister Ashwini Vaishnaw recently said India might be able to create its high-end computing chipset in the next three to five years, confirming talks with NVIDIA to co-develop GPUs.
Cadence will support this effort by providing chip design tools to the government and Indian companies.
“If any company designs a GPU, they will use our software and tools, which are essential for chip design. So, we look forward to supporting such an endeavour by making these tools available,” Ahuja said. “The right semiconductor strategy for India will be design-led manufacturing.”
Cadence is a major chip designer, which provide tools and software for design and works with leading semiconductor companies such as Intel, AMD, Qualcomm, and others.
Its chip design tools are already available through the national EDA grid, established under India’s Design-Linked Incentive (DLI) plan within the India Semiconductor Mission (ISM).
“Our global CEO meets the minister regularly and advises him on the best way to build this capability and bootstrap the semiconductor ecosystem in India,” Ahuja added, emphasising Cadence’s role in connecting the government with key industry players.
Growing business potential in India
Cadence also sees business opportunities as medium and large companies such as L&T Semiconductor Technologies and HRDWYR enter chip designing.
“For India, chip design is the greatest opportunity to create value for the industry. While manufacturing is important, it is a highly capital-intensive business with significant challenges in profitability. Only a few companies such as TSMC and Samsung have succeeded,” Ahuja said.
The government needs to enhance DLI incentives to attract high-quality proposals from startups, he said.
“There are active discussions about certain incentive enhancements under the new DLI scheme,” he said. “There are genuinely serious players, but the current incentive structure is not sufficient for them.”
Of the approximately 60 proposals submitted to the Ministry of Electronics and IT (MeitY) for DLI subsidies, only around 20 companies have met the criteria and only a few have secured fabrication orders for their design prototypes.
The ministry has set a target of funding 100 startups as part of its semiconductor push.
The government is now working on the next phase of the semiconductor incentive scheme, ISM 2.0, to increase funding and allow multinational and large Indian companies to participate in the programme.
Workforce expansion
Cadence is leveraging its Indian workforce of 4,300 employees (out of a global workforce of over 12,000) primarily for research and development.
“We have been expanding our presence in India every year. Going forward, we will grow in India disproportionately, meaning faster than the company’s overall headcount growth. We have grown at a 10 percent CAGR over the past decade,” Ahuja said.
It has been working with MeitY on the Chips to Startup programme, providing electronic design automation (EDA) tools to universities across India. The initiative aims to train 85,000 chip-design engineers by 2027. Cadence has collaborated with Indian Institute of Technology (IIT)-Delhi, IIT-Hyderabad, and Punjab Engineering College to develop a skilled workforce, offering students exposure to global industry leaders.
Cadence is also aligned with C-DAC’s "Chip-in" initiative, which enables universities to engage in R&D for chip design while fostering startup creation in the semiconductor sector.
It has also been involved in the Specialized Manpower Development Program (SMDP) in VLSI Design (Phases I and II) since its inception in 1998, focusing on talent development.
“Collaboration with the government is an ongoing process and a long-haul journey. We want to see India’s design ecosystem flourish,” Ahuja said.
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