A committee under the Ministry of Electronics and Information Technology (MeitY) has recommended the government to set up the India Semiconductor Research Centre (ISRC) at a cost of $2.5-3 billion, with the aim to make India a global foundry supplier for semiconductors, packagers and integrated systems from design to products.
The government envisions ISRC as a world-class research institution focusing on semiconductor processes, advanced packaging, compound semiconductors and Fabless design and EDA tools. The Semiconductor Laboratory in Mohali will also be modernised to drive innovation while co-locating with the ISRC.
These recommendations were made in a report of the India Semiconductor R&D Committee that was submitted to Minister of State for Electronics and Information Technology Rajeev Chandrasekhar on October 20. Chandrasekhar told PTI that the government will start setting up the research centre in 2024 in collaboration with the industry and academia.
The committee's member includes Randhir Thakur of Tata Electronics, Hem Takiar of Micron Technology, CEO of the Indian Semiconductor Mission, professors from IIT Bombay, Kanpur and Madras, officials from Meity and other members of the industry.
Chandrasekhar said, “After months of dedicated research, the India Semiconductor R&D Committee has laid out a roadmap of ISRC, realising what can be the architectural design of PM Modi’s vision for the semiconductor ecosystem.
"After being absent from the semiconductor ecosystem for decades and missing many opportunities, we are now playing catch up. This institution will be a core institution in India’s growing capabilities in semiconductors. It will be the Indian equivalent of IMEC, Nano Tech, ITRI and the MIT Micro-electronic labs which have been the pioneers of every cutting-edge technology in the world," he added.
Focus on semiconductor infra
The report, a copy of which Moneycontrol has seen, estimates setting up a 1-1.5 lakh sq ft clean room for Si fab and 20,000-30,000 sq ft for advanced packaging.
"Such a centre would nurture and expand chip design, fabrication and packaging R&D, encourage indigenous innovation for global leadership, and provide a platform for early scaled-up concept verification and workload-based prototyping such as next-generation chipset based packaging for AI, 5G/6G, IoT/manufacturing 4.0," the report read.
This along with other capital expenditures, for the first three years, would cost around $2.5-$3 billion. The committee estimates the annual operating expense for maintaining the research centre to be around $250 million - $ 500 million.
R&D and education
"In the 2-5 years' horizon, the theme for the ISRC will have to also incorporate completion of establishment of new R&D and education infrastructure, and implementation of technologies that will provide a wider range of capabilities and research offerings for the ISRC including potential for integrated packaging and system pilots," the report read.
As part of setting up fostering R&D, education and industry partnerships in semiconductors, the committee has estimated that it will cost the government Rs 3,200 crore over a five-year period. The total share of the industry will be around Rs 680 crore, the report read.
The report also says that a number of companies including, Vedanta, Samsung, Sahasra Semi, Qualcomm, Micron, Microsoft, Intel and others have expressed interest in partnering for research and development, education and talent development as part of the semiconductor research centre.
Foundational pillars
The committee has recommended that the ISRC have a minimum of 12 boards of directors. The Board of Directors will appoint a CEO for the ISRC. Under the CEO and Board of Directors, will be the Technica Advisory Board comprising members from government, industry and academia. The governance structure of ISRC would also include a management team.
The Technology advisory board will be tasked with putting out a roadmap of the ISRC covering four foundational research pillars -- advanced silicon, packaging R&D, compound/power semiconductors, chip design and EDA.
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