Altera unveils Plug & Play Signal Integrity Technology

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Altera Corporation (NASDAQ: ALTR) today announced its Plug & Play Signal Integrity technology, an innovative system solution that is enabled by the latest Quartus^® II design software and available now in production Stratix^® II GX FPGAs. Plug & Play Signal Integrity redefines FPGA use in high-performance systems by enabling a single card configuration to be plugged into any designated system slot while under system power.

 

Altera's Plug & Play Signal Integrity technology is an exclusive combination of low-power linear adaptive equalization technology-Altera's new Adaptive Dispersion Compensation Engine (ADCE)-and the hot-socketing capability found in every Altera^® FPGA. When hot-swapping a single card configuration in a system, the ADCE automatically monitors and adjusts itself for interconnect loss and environmental variations to provide the highest system performance and data reliability available in the industry today.

 

"Altera continues to deliver FPGA transceiver innovation to customers by providing system designers with the only plug-and-play signal integrity capability available in an FPGA," said Louie Leung, marketing director at Altera. "Our FPGAs' ability to plug into a powered system and automatically adjust to varying system and environmental conditions allows our customers to reduce inventories, simplify maintenance procedures and shorten time to market. The ADCE itself significantly reduces the tedious characterization effort that is the result of high-speed systems having varying link characteristics across card slots."

 

Plug & Play Signal Integrity provides designers and system architects with production-qualified, hot-socketable Stratix II GX FPGAs that now can actively monitor and automatically compensate for signal degradation in multi-gigabit system interconnects due to manufacturing, voltage, temperature, and design variations. Altera's Plug & Play Signal Integrity solution continuously adjusts equalizer settings for each of up to 20 receivers found in the Stratix II GX FPGA family to provide the best eye opening for non-return-to-zero (NRZ) signals operating between 2.5 Gbps and 6.375 Gbps, significantly improving system reliability, performance, and bit error rate (BER).

 

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